Semiconductor devices are used in many electronic and other applications. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.
Semiconductor devices are packaged using various packaging technologies. One way of packaging semiconductor devices is wafer level packaging, which refers to a particular packaging technology where an integrated circuit is packaged at the wafer level. In wafer level packaging, an integrated circuit is packaged at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. The chips are packaged directly on the wafer and dicing of the wafer takes place after the chips are packaged. Wafer level packaging may be used to manufacture chip scale packages.
A package formed using such wafer level packaging, i.e., a wafer level package (WLP) is a promising solution for high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements.
Wafer level packaging is a true chip-scale packaging technology, as the resulting package is about the same size as the die. By extending the wafer fab processes to include device interconnection and device protection processes, wafer-level packaging integrates wafer fab processes with packaging and possibly test and burn-in at wafer level, streamlining and reducing manufacturing costs.
Embedded wafer level packaging is an enhancement of the standard wafer level packaging in which the packaging is realized on an artificial wafer. A standard wafer is diced and the singulated chips are placed on a carrier. The distances between the chips on the carrier may be chosen freely. The gaps around the chips may be filled with an encapsulation material to form an artificial wafer. The artificial wafer is processed to manufacture packages comprising the chips and a surrounding fan-out area. Interconnect elements may be realized on the chip and the fan-out area forming an embedded wafer level ball grid array (eWLB) package.